Handle lds on vti domain and fix some bugs on vti domain

Signed-off-by: Anthony Xu <anthony.xu@intel.com>

diff --git a/xen/arch/ia64/vmx/vlsapic.c b/xen/arch/ia64/vmx/vlsapic.c
index 340bdd40c410361b22a452bcf239892bae49e528..3b378d07b46528c6df3afe8b4ba55dc06ffb8124 100644 (file)
--- a/xen/arch/ia64/vmx/vlsapic.c
+++ b/xen/arch/ia64/vmx/vlsapic.c
@@ -529,7 +529,7 @@ int vmx_check_pending_irq(VCPU *vcpu)
     int injected=0;
     uint64_t    isr;
     IA64_PSR    vpsr;
-
+    REGS *regs=vcpu_regs(vcpu);
     local_irq_save(spsr);
     h_pending = highest_pending_irq(vcpu);
     if ( h_pending == NULL_VECTOR ) goto chk_irq_exit;
@@ -541,7 +541,7 @@ int vmx_check_pending_irq(VCPU *vcpu)
         isr = vpsr.val & IA64_PSR_RI;
         if ( !vpsr.ic )
             panic("Interrupt when IC=0\n");
-        vmx_reflect_interruption(0,isr,0, 12 ); // EXT IRQ
+        vmx_reflect_interruption(0,isr,0, 12, regs ); // EXT IRQ
         injected = 1;
     }
     else if ( mask == IRQ_MASKED_BY_INSVC ) {
@@ -601,13 +601,13 @@ static void generate_exirq(VCPU *vcpu)
 {
     IA64_PSR    vpsr;
     uint64_t    isr;
-    
+    REGS *regs=vcpu_regs(vcpu);
     vpsr.val = vmx_vcpu_get_psr(vcpu);
     update_vhpi(vcpu, NULL_VECTOR);
     isr = vpsr.val & IA64_PSR_RI;
     if ( !vpsr.ic )
         panic("Interrupt when IC=0\n");
-    vmx_reflect_interruption(0,isr,0, 12 ); // EXT IRQ
+    vmx_reflect_interruption(0,isr,0, 12, regs); // EXT IRQ
 }
 
 vhpi_detection(VCPU *vcpu)

diff --git a/xen/arch/ia64/vmx/vmmu.c b/xen/arch/ia64/vmx/vmmu.c
index 07acfa3bd9dc043aa14e8808fff5a7627e515e65..f6dc9c2fd897f064f9c519ee88b3b38df67e6b36 100644 (file)
--- a/xen/arch/ia64/vmx/vmmu.c
+++ b/xen/arch/ia64/vmx/vmmu.c
@@ -438,20 +438,23 @@ fetch_code(VCPU *vcpu, u64 gip, u64 *code)
     thash_data_t    *tlb;
     ia64_rr vrr;
     u64     mfn;
-    
+
     if ( !(VCPU(vcpu, vpsr) & IA64_PSR_IT) ) {   // I-side physical mode
         gpip = gip;
     }
     else {
         vmx_vcpu_get_rr(vcpu, gip, &vrr.rrval);
-        tlb = vtlb_lookup_ex (vmx_vcpu_get_vtlb(vcpu), 
+        tlb = vtlb_lookup_ex (vmx_vcpu_get_vtlb(vcpu),
                 vrr.rid, gip, ISIDE_TLB );
-        if ( tlb == NULL ) panic("No entry found in ITLB\n");
+        if( tlb == NULL )
+             tlb = vtlb_lookup_ex (vmx_vcpu_get_vtlb(vcpu),
+                vrr.rid, gip, DSIDE_TLB );
+        if ( tlb == NULL ) panic("No entry found in ITLB and DTLB\n");
         gpip = (tlb->ppn << 12) | ( gip & (PSIZE(tlb->ps)-1) );
     }
     mfn = __gpfn_to_mfn(vcpu->domain, gpip >>PAGE_SHIFT);
     if ( mfn == INVALID_MFN ) return 0;
-    
+ 
     mpa = (gpip & (PAGE_SIZE-1)) | (mfn<<PAGE_SHIFT);
     *code = *(u64*)__va(mpa);
     return 1;

diff --git a/xen/arch/ia64/vmx/vmx_process.c b/xen/arch/ia64/vmx/vmx_process.c
index 170a24f6b5b510e8a8c9f0c9b433e4e90e3fa81c..1b187b153fb5be31c266387646862f3616a68385 100644 (file)
--- a/xen/arch/ia64/vmx/vmx_process.c
+++ b/xen/arch/ia64/vmx/vmx_process.c
@@ -47,6 +47,7 @@
 #include <asm/kregs.h>
 #include <asm/vmx.h>
 #include <asm/vmx_mm_def.h>
+#include <asm/vmx_phy_mode.h>
 #include <xen/mm.h>
 /* reset all PSR field to 0, except up,mfl,mfh,pk,dt,rt,mc,it */
 #define INITIAL_PSR_VALUE_AT_INTERRUPTION 0x0000001808028034
@@ -267,6 +268,12 @@ void leave_hypervisor_tail(struct pt_regs *regs)
 
 extern ia64_rr vmx_vcpu_rr(VCPU *vcpu,UINT64 vadr);
 
+static int vmx_handle_lds(REGS* regs)
+{
+    regs->cr_ipsr |=IA64_PSR_ED;
+    return IA64_FAULT;
+}
+
 /* We came here because the H/W VHPT walker failed to find an entry */
 void vmx_hpw_miss(u64 vadr , u64 vec, REGS* regs)
 {
@@ -294,18 +301,19 @@ void vmx_hpw_miss(u64 vadr , u64 vec, REGS* regs)
         return;
     }
 */
-
-    if((vec==1)&&(!vpsr.it)){
-        physical_itlb_miss(v, vadr);
-        return;
-    }
-    if((vec==2)&&(!vpsr.dt)){
-        if(v->domain!=dom0&&__gpfn_is_io(v->domain,(vadr<<1)>>(PAGE_SHIFT+1))){
-            emulate_io_inst(v,((vadr<<1)>>1),4);   //  UC
-        }else{
-            physical_dtlb_miss(v, vadr);
+    if(is_physical_mode(v)&&(!(vadr<<1>>62))){
+        if(vec==1){
+            physical_itlb_miss(v, vadr);
+            return;
+        }
+        if(vec==2){
+            if(v->domain!=dom0&&__gpfn_is_io(v->domain,(vadr<<1)>>(PAGE_SHIFT+1))){
+                emulate_io_inst(v,((vadr<<1)>>1),4);   //  UC
+            }else{
+                physical_dtlb_miss(v, vadr);
+            }
+            return;
         }
-        return;
     }
     vrr = vmx_vcpu_rr(v, vadr);
     if(vec == 1) type = ISIDE_TLB;
@@ -336,7 +344,8 @@ void vmx_hpw_miss(u64 vadr , u64 vec, REGS* regs)
             } else{
                 if(misr.sp){
                     //TODO  lds emulation
-                    panic("Don't support speculation load");
+                    //panic("Don't support speculation load");
+                    return vmx_handle_lds(regs);
                 }else{
                     nested_dtlb(v);
                     return IA64_FAULT;
@@ -353,8 +362,9 @@ void vmx_hpw_miss(u64 vadr , u64 vec, REGS* regs)
                     return IA64_FAULT;
                 }else{
                     if(misr.sp){
-                        //TODO  lds emulation
-                        panic("Don't support speculation load");
+                    //TODO  lds emulation
+                    //panic("Don't support speculation load");
+                    return vmx_handle_lds(regs);
                     }else{
                         nested_dtlb(v);
                         return IA64_FAULT;
@@ -367,8 +377,9 @@ void vmx_hpw_miss(u64 vadr , u64 vec, REGS* regs)
                     return IA64_FAULT;
                 }else{
                     if(misr.sp){
-                        //TODO  lds emulation
-                        panic("Don't support speculation load");
+                    //TODO  lds emulation
+                    //panic("Don't support speculation load");
+                    return vmx_handle_lds(regs);
                     }else{
                         nested_dtlb(v);
                         return IA64_FAULT;

diff --git a/xen/arch/ia64/vmx/vmx_virt.c b/xen/arch/ia64/vmx/vmx_virt.c
index b118ac03cdb7899568de0972ff38d876d019affa..74c1d592913ac4dfc5b27a063a55c457664b1d04 100644 (file)
--- a/xen/arch/ia64/vmx/vmx_virt.c
+++ b/xen/arch/ia64/vmx/vmx_virt.c
@@ -835,6 +835,7 @@ IA64FAULT vmx_emul_mov_to_rr(VCPU *vcpu, INST64 inst)
 
 IA64FAULT vmx_emul_mov_to_dbr(VCPU *vcpu, INST64 inst)
 {
+    return IA64_NO_FAULT;
     u64 r3,r2;
 #ifdef  CHECK_FAULT
     IA64_PSR vpsr;
@@ -858,6 +859,7 @@ IA64FAULT vmx_emul_mov_to_dbr(VCPU *vcpu, INST64 inst)
 
 IA64FAULT vmx_emul_mov_to_ibr(VCPU *vcpu, INST64 inst)
 {
+    return IA64_NO_FAULT;
     u64 r3,r2;
 #ifdef  CHECK_FAULT
     IA64_PSR vpsr;
@@ -1272,8 +1274,7 @@ IA64FAULT vmx_emul_mov_from_cr(VCPU *vcpu, INST64 inst)
         case 74:return vmx_cr_get(cmcv);
         case 80:return vmx_cr_get(lrr0);
         case 81:return vmx_cr_get(lrr1);
-        default:
-            panic("Read reserved cr register");
+        default: return IA64_NO_FAULT;
     }
 }
 

diff --git a/xen/arch/ia64/vmx/vtlb.c b/xen/arch/ia64/vmx/vtlb.c
index 2d726efe2182475bb33cea6ba762938f5ed0014c..d6ae1a6220bf9407cf852c38a13265f5ad561dd5 100644 (file)
--- a/xen/arch/ia64/vmx/vtlb.c
+++ b/xen/arch/ia64/vmx/vtlb.c
@@ -391,6 +391,7 @@ void vtlb_insert(thash_cb_t *hcb, thash_data_t *entry, u64 va)
 #if 1
     vrr=vmx_vcpu_rr(current, va);
     if (vrr.ps != entry->ps) {
+        machine_tlb_insert(hcb->vcpu, entry);
        printk("not preferred ps with va: 0x%lx\n", va);
        return;
     }